In recent years, research and development of a nonvolatile memory are being actively carried out. What particularly attracts attention is a resistance change memory that stores information as a resistance value of a memory element. The resistance change memory is exemplified by a magnetic random access memory (MRAM) that performs data writing by using magnetic field, a phase change memory (ovonic unified memory: OUM) that performs data writing by using heat, a resistance random access memory (Resistance RAM: RRAM) that performs data writing by using voltage.
Many of the nonvolatile resistance change memories are expected to be alternatives to an existing storage or a volatile RAM. For example, the MRAM, which is characterized by a high-speed operation and a large number of rewritable times, is expected to be alternative to a volatile RAM such as a DRAM, an SRAM or the like. However, since it uses a peculiar read principle that senses resistance, some problems are to be resolved in circuit in order to satisfy input-output compatibility with the existing devices.
For example, many of the existing RAMs are provided with a high-speed read operation called page mode or burst mode, as is well known to those skilled in the art. In such the read operation, data of memory cells at a plurality of addresses are read out at a time and the result is sequentially output with high speed. To achieve such the mode, it is necessary to place a large number of read circuits (sense amplifiers). Considering a case where input-output pins are 16 bits and a 16-words burst read operation is carried out, for example, at least 256 read circuits are necessary. As for the MRAM, however, an area of the read circuit is large because data signals of “0” and “1” are small, and thus it is not easy to place a large number of read circuits.
A technique relating to a read circuit of an MRAM is disclosed, for example, in a document: J. DeBrosse, et al., “A High-Speed 128-kb MRAM Core for Future Universal Memory Applications”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 4, No. 4, APRIL 2004, pp. 678-683. FIG. 1 shows a configuration of the MRAM that includes the read circuit according to the relevant technique. The MRAM is provided with a memory array 108, a row decoder 107, a column decoder 106, and read circuits 105a and 105b. The memory array 108 has a plurality of read word lines 121, a plurality of bit lines 122, a plurality of reference bit lines 122r, a plurality of memory cells 131, and a plurality of reference cells 132a and 132b. 
The plurality of read word lines 121 extend in an X-direction. The plurality of bit lines 122 extend in a Y-direction. The plurality of reference bit lines 122r extend in the Y-direction. The plurality of memory cells 131 are provided at respective intersections of the plurality of read word lines 121 and the plurality of bit lines 122. The plurality of reference cells 132b and 132a are provided at respective intersections of the plurality of read word lines 121 and the plurality of reference bit lines 122r. In a read operation, the row decoder 107 selects a selected read word line 121 from the plurality of read word lines 121. In the read operation, the column decoder 106 selects selected bit lines 122 and the reference bit lines 122r from the plurality of bit lines 122 and 122r. Consequently, memory cells 131 provided at respective intersections of the selected read word line 121 and the selected bit lines 122 are selected as selected cells 131 at the time of the read operation. Also, the reference cells 132b and 132a provided at respective intersections of the selected read word line 121 and the reference bit lines 122r are selected as selected reference cells 132b and 132a. The selected bit lines 122 and the reference bit lines 122r are connected to the read circuits 105b and 105a through the column decoder 106. As a result, data of the selected cells 131 and the reference cells 132b and 132a are read by the read circuits 105b and 105a. 
In the above MRAM, the reference cell 132b has a resistance value Rmin related to data “0”, the reference cell 132a has a resistance value Rmax related to data “1”, and the two read circuits 105b and 105a are provided for the respective reference cells 132b and 132a. The read circuits 105b and 105a have current-voltage conversion circuits 102b and 102a and sense amplifiers 104b and 104a, respectively. The current-voltage conversion circuit 102b (102a) outputs a sense voltage Vs that is proportional to a current flowing through the memory cell 131 and a reference voltage Vref that is proportional to a current flowing through the reference cell 132b (132a). The sense amplifier 104b (104a) makes a comparison between the sense voltage Vs and the reference voltage Vref. Inputs/outputs on the sides of reference cells of the current-voltage conversion circuits 102b and 102a are short-circuited to each other between the read circuits 105b and 105a. It is therefore possible to set the reference voltage Vref at an intermediate voltage between the sense voltage Vs(0) corresponding to data “0” and the sense voltage Vs(1) corresponding to data “1”.
According to the above configuration, the reference cell 132b, 132a is necessary for every read circuit 105b, 105a. Therefore, when a large number of read circuits 105b, 105a are placed, an occupancy rate of the memory cells 131 which a user can freely use for data reading/writing is decreased. To avoid this problem, a circuit technique is essential with which the reference cell 132b, 132a can be used by a plurality of read circuits. In this case, each reference voltage Vref is interfered and thus fluctuated, by the amplification operation of the sense amplifier 104b, 104a in every read circuit 105b, 105a. Since the data signals of “0” and “1” are small in the MRAM, the fluctuation due to the interference cannot be ignored. The above-mentioned interference greatly deteriorates reliability of data reading in the MRAM. Although this problem can be avoided to a certain extent by using a sense amplifier with high-impedance input, a circuit system of the sense amplifier is limited. In addition, when a large number of sense amplifiers operate simultaneously, the read reliability is deteriorated due to influence of noises of power supply voltage and so forth. As explained above, it is not easy to place a large number of read circuits in the MRAM. A technique is desired which can make a large number of read circuits operate simultaneously without deteriorating the read reliability.
Moreover, in the sense operation, the memory cell 131 and the reference cell 132b, 132a are electrically connected to each other through the sense amplifier 104b, 104a. For this reason, an improper voltage may be applied to the memory cell 131 and the reference cell 132b, 132a due to the amplification operation of the sense amplifier 104b, 104a. A technique is desired which prevents that the improper voltage is applied to the memory cell 131 and the reference cell 132b, 132a in the sense operation.
In the above description, the MRAM is explained as an example. Similarly, such the technique is also desired to other resistance change memories that are based on the similar read principle. By the way, the followings are known as other relevant techniques relating to the nonvolatile memory.
Japanese Laid Open Patent Application JP-P2004-39150A discloses a technique to eliminate influence of sneak path current and improve reliability of detecting data stored in memory cells of an MRAM. A read circuit of the MRAM includes an offset elimination circuit and a data detection circuit. The offset elimination circuit generates a current difference signal that corresponds to difference between a sense current flowing through a selected bit line when a voltage is applied between a selected word line and the selected bit line and an offset component current flowing through a dummy bit line when a voltage is applied between the selected word line and the dummy bit line. Based on the current difference signal, the data detection circuit detects memory data stored in a selected cell provided between the selected word line and the selected bit line.
Japanese Laid Open Patent Application JP-A-Heisei 7-192476 discloses a nonvolatile ferroelectric memory. In the nonvolatile ferroelectric memory, a reference potential generation unit generates a reference potential based on signal potentials of logics 1 and 0, and a potential retention unit holds the reference potential. In a read operation, a potential supply unit generates the reference potential to one data line based on the held potential. Information is detected through a comparison between a signal potential read out to the other data line and the reference potential.
Japanese Laid Open Patent Application JP-P2003-151262A discloses a method of reading data from an MRAM. The method includes a step of flowing a first read current through a memory cell, a step of writing a write data that has a predetermined value into the memory cell, a step of flowing a second read current through the memory cell into which the write data is written, and a step of judging data of the memory cell by detecting difference between the first and second read currents.
Japanese Laid Open Patent Application JP-A-Heisei 11-26727 discloses a nonvolatile semiconductor memory. The nonvolatile semiconductor memory has a memory cell consisting of a MOS transistor having a floating gate, a sense amplifier, a reference cell having the same structure as the memory cell, a control voltage generation circuit that generates a reference cell control voltage applied to the reference cell, and a reference voltage generation circuit that generates a reference voltage from the output of the reference cell. The floating gate and a control gate of the reference cell are short-circuited to each other.
National publication of the translated version of PCT application JP-P2002-533863 discloses an MRAM. The MRAM has a magnetic memory cell connected in series to a first conductive wiring, a reference magnetic memory cell connected in series to a second conductive wiring, and a resistance element connected in series to the reference magnetic memory cell. The magnetic memory cell has a magneto-resistance that is switched between a minimum value and a maximum value. The reference memory cell has a predetermined magneto-resistance. Total resistance of the reference magnetic memory cell and the resistance element is set between the minimum value and the maximum value.